RAD 6000-SC Interfaces
Memory Bus
- 64 data bits wide plus 8 ECC bits (direct to HMC)
- 24 address bits (interface to CELLA)
- 7 control signals (interface to CELLA)
RSC Input and Output Bus
- 32 multiplexed address and data bits
- 1 parity bit for address/data
- 14 control signals
- 17 external interrupts
- Full interface to RBI gate array
COP Diagnostic Serial Bus
- 9 bits of control, clock and data
- Interface only to external test equipment