RAD 6000-SC Components Descriptions
Memory Interface Unit Organizes accesses to and from local memory and provides RAM data to the cache unit
Cache Unit Coordinates accesses to the cache
Instruction Buffer Unit Pulls instructions from the cache and dispatches instructions to the fixed point, floating point, and in page fetcher (branch instructions)
Fixed/Floating Point Provides separate pipelined execution units for their respective instruction types
I/O Sequencer Interfaces to RSC I/O bus and provides for initialization of the processor at start up
Pipeline Control Unit Controls proper sequencing and interlocking operation of the other processor functional units
COP Unit Interfaces with external test equipment and assists in the resetting and initialization of the processor registers and arrays