CELLA

• Decode and Handshake

  • Decodes RSC memory control signals to determine current operation
  • Generates handshaking signals to the RSC
  • Sends control information to read/write state machines
  • Suspends current command during RSC ECC processing

• DRAM Control Logic

  • Directs sequencing of LUNA control signals for memory read and write operations
  • Selects DRAM row based on input from pipelined address register and IPL/refresh logic

• IPL and Refresh Logic

  • Performs pump-up cycles after POR
  • Provides 2048 refresh cycles every 32 milliseconds

• Pipelined Address Register - buffers incoming RSC memory address while previous command completes

• DRAM Row/Address Address Mux

  • Buffers current DRAM address
  • Selects and drives appropriate row/column addresses to the LUNA-C

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