Serial Interface - Transmitter State Diagram

IDLE

SYSRESET/

Shift out a

0 (start)

DSR/

Shift out data

bits (8 bits)

Shift out a

0 (stop)

DATA TO S/R

TXR=0

• State Diagram Variables

  • WR/
    • I/O write to TX buffer
  • RD/
    • I/O read from status buffer
  • TXR/
    • Signal from shift register machine indicating it has loaded current word
  • DRDY
    • Signal to shift register machine and status buffer indicating TX buffer is full
  • TOF
    • Overflow signal, set if CPU attempts to transfer data into a full buffer, provided to CPU in status register, cleared by read of status register

DRDY

!DRDY

IDLE

TOF,DRDY = 0

WR/

Load Buffer

DRDY = 1

!WR/

WR/ &

TXR

!TXR

!WR/

ERROR

TOF = 1

RD/

RD/

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