Asynchronous Receiver State Machine

IDLE

DSR/,OF/,FR =1

SYSRESET/

Shift in

bit #1

DSR/

Wait 24

clocks

RX

!RX

Shift in

bit #2

DSR/

Wait 16

clocks

DSR/

Wait 16

clocks

Shift in

bit #3

DSR/

Wait 16

clocks

Shift in

bit #4

DSR/

Wait 16

clocks

Shift in

bit #5

DSR/

Wait 16

clocks

Shift in

bit #6

DSR/

Wait 16

clocks

Shift in

bit #7

DSR/

Wait 16

clocks

Shift in

bit #8

DSR/

Wait 16

clocks

Shift in

Stop Bit (Bit 9)

FR/=0

RX &

!STOP &

EMPTY

STOP

OF/=0

RX &

!STOP &

!EMPTY

RX &

EMPTY

!RX &

!STOP &

!EMPTY

!RX

Data to Buffer

DSR/=0

EMPTY

RX &

!EMPTY

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