Double Buffer Access - State Diagram

IDLE

SYSRESET/

Perform R/W

WRCOMP = 1

DSR/

Prioritze and

Grant

!DSR/ +

CPUREQ

!DSR/ +

CPUREQ

• State Diagram Variables
  • DSR/
    • Six different Data Set Ready signals, one from each SI
  • CPUREQ
    • Request from CPU to read from double buffer memory
  • WRCOMP and RDCOMP
    • Handshaking from machine to either one of the serial interfaces, or the VME interface to indicate the action is complete
  • DRDY
    • Signal to shift register machine and status buffer indicating TX buffer is full

Previous slide

Next slide

Back to first slide

View graphic version